A programmable logic device (PLD) is a configurable integrated circuit used to implement a custom logic function. Examples of PLDs include devices such as, but not limited to, a programmable logic array (PLA), a field programmable gate array (FPGA), and an erasable and complex PLD. PLDs have been used to implement memory interface controllers for memory interfaces such as double data rate (DDR) interfaces employed in synchronous dynamic random access memory (SDRAM), for example.
In a basic DDR implementation, a clock or strobe (DQS) signal is used to control the timing of the transfer of input/output (I/O) data (DQ). The DDR3 specification requires a preamble period, defined as greater than or equal to 90 percent of a clock period, during which the DQS signal is driven low before data transfer. Similarly, after the last falling edge of the DQS signal, the DDR3 specification defines a post-amble period, defined as greater than or equal to 40 percent of the clock period, during which the DQS signal is again driven low. However, the DQS signal has periods of tri-state during which its value is indeterminate (between high and low). The challenge is to gate the DQS signal to periods in which the signal is not tri-stated, to prevent spurious signals from being fed into the physical interface circuitry (PHY) capture and resynchronization logic.
In one conventional implementation, the DQS signal is sampled using the DQS gating enable signal, but this technique can only sample the DQS signal at the end of a read burst (at the end of the period between the preamble and the post-amble). In another conventional implementation, multiple DQS edges are sampled utilizing a free running clock, but this technique requires significant circuit duplication to provide phase control over both the free running clock and the DQS enable signal.
Furthermore, only the rising edge of the DQS signal is conventionally tracked based on samples taken, with the falling edge of the DQS enable signal used for ungating. This enables proper adjustments to be made to the DQS enable signal to track low-frequency variation in round-trip delay that affects the ungating timing window (defined with respect to rising DQS edges). However, because the falling edges of DQS are not tracked, an implicit assumption is made that the DQS enable signal used for gating needs the same adjustments as the signal used for ungating. That is, the memory duty cycle distortion (DCD) variation that affects the relative position of the gating and ungating timing windows is not compensated.